# Xilinx CORE Generator 6.1i
# Username = RAUF
# COREGenPath = I:\Xilinx\coregen
# ProjectPath = I:\8051_CORDIC_UART
# ExpandedProjectPath = I:\8051_CORDIC_UART
# OverwriteFiles = true
# Core name: cordic
# Number of Primitives in design: 1441
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 512
# Number of LUTs used in design: 512
# Number of REG used in design: 456
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Spartan3
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT CORDIC Spartan3 Xilinx,_Inc. 2.0
CSET synchronization_enable = No_Override
CSET create_rpm = true
CSET register_inputs = true
CSET sclr = false
CSET architectural_configuration = Word_Serial
CSET phase_format = Radians
CSET nd = true
CSET data_format = SignedFraction
CSET register_outputs = true
CSET rdy = true
CSET aclr = false
CSET ce = false
CSET y_out = true
CSET component_name = cordic
CSET pipelining_mode = Maximum
CSET compensation_scaling = CCM_Scale_Compensation
CSET input_width = 8
CSET round_mode = Round_Pos_Neg_Inf
CSET iterations = 0
CSET precision = 0
CSET functional_selection = Rotate
CSET output_width = 8
CSET phase_output = false
CSET coarse_rotation = true
CSET x_out = true
GENERATE
