--
-- Copyright (c) 2001 Koay Kah Hoe.  Permission to copy is granted
-- provided that this header remains intact.  This code is provided
-- with no warranties.
--
-- Version : 1.0
--

-------------------------------------------------------------------------------

-- Synchronize: Library module created by VHDL Module Generator
--
-- Synchronize
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity Synchronize is
	port (
		ASYN : in STD_LOGIC;
		SYNC : out STD_LOGIC;
		CLK : in STD_LOGIC
	);
end Synchronize;

architecture Synchronize_arch of Synchronize is

begin
	process (CLK)
	begin
		if rising_edge(CLK) then
			SYNC <= ASYN;
		end if;
	end process;
end Synchronize_arch;

