library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity system is
	port (rst_externo 	: in  STD_LOGIC;	
         clk          	: in  STD_LOGIC;
	    P_A			: out std_logic;
	    P_B			: out std_logic;
	    P_C			: out std_logic;
	    P_D			: out std_logic;
	    P_E			: out std_logic;
	    P_F			: out std_logic;
	    P_G			: out std_logic;
	    P_AN3			: out std_logic;
	    P_AN2			: out std_logic;
	    P_AN1			: out std_logic;
	    P_AN0			: out std_logic;	    	    	    
	    P_LD7			: out std_logic;
	    P_BTN2		: in std_logic;
	    P_BTN1		: in std_logic;
	    P_BTN0		: in std_logic;
	    P_DP			: out std_logic;
	    TX			: out std_logic;
	    RX			: in std_logic);

-- p0_in :	ack rdy P_BTN2 P_BTN1 P_BTN0 - - -
-- p0_out:	we adr stb nd P_LD7 P_AN1 P_AN0 ModoCORDIC
-- p1_in :	x'
-- p1_out:	x / P_A P_B P_C P_D P_E P_F P_G - (ModoCORDIC=0)   
-- p2_in :	y'
-- p2_out: 	y / dato_uart_in (ModoCORDIC=0)
-- p3_in :	dato_uart_out
-- p3_out: 	angulo 


end system;

architecture Behavioral of system is

component UART is
  generic(BRDIVISOR: INTEGER range 0 to 65535 := 130); -- Baud rate divisor
  port (
-- Wishbone signals
     WB_CLK_I : in  std_logic;  -- clock
     WB_RST_I : in  std_logic;  -- Reset input
     WB_ADR_I : in  std_logic_vector(1 downto 0); -- Adress bus          
     WB_DAT_I : in  std_logic_vector(7 downto 0); -- DataIn Bus
     WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
     WB_WE_I  : in  std_logic;  -- Write Enable
     WB_STB_I : in  std_logic;  -- Strobe
     WB_ACK_O : out std_logic;	-- Acknowledge
-- process signals     
     IntTx_O  : out std_logic;  -- Transmit interrupt: indicate waiting for Byte
     IntRx_O  : out std_logic;  -- Receive interrupt: indicate Byte received
     BR_Clk_I : in  std_logic;  -- Clock used for Transmit/Receive
     TxD_PAD_O: out std_logic;  -- Tx RS232 Line
     RxD_PAD_I: in  std_logic);  -- Rx RS232 Line     
end component;

component I8051_ALL is
	port (rst_lo       : in  STD_LOGIC;	
         clk          : in  STD_LOGIC;
	    p0_in        : in  UNSIGNED (7 downto 0);
         p0_out       : out UNSIGNED (7 downto 0);
         p1_in        : in  UNSIGNED (7 downto 0);
         p1_out       : out UNSIGNED (7 downto 0);
         p2_in        : in  UNSIGNED (7 downto 0);
         p2_out       : out UNSIGNED (7 downto 0);
         p3_in        : in  UNSIGNED (7 downto 0);
         p3_out       : out UNSIGNED (7 downto 0)
	);
end component;


	COMPONENT clk_div
	PORT(
		RST_IN : IN std_logic;
		CLKIN_IN : IN std_logic;          
		LOCKED_OUT : OUT std_logic;
		CLKDV_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLKIN_IBUFG_OUT : OUT std_logic
		);
	END COMPONENT;

	signal a,c: std_logic;
	signal clk0: std_logic;
	signal clk_out: std_logic;
	signal rst_lo: std_logic;



	component cordic

	port (
		x_in: IN std_logic_VECTOR(7 downto 0);
		y_in: IN std_logic_VECTOR(7 downto 0);
		phase_in: IN std_logic_VECTOR(7 downto 0);
		nd: IN std_logic;
		x_out: OUT std_logic_VECTOR(7 downto 0);
		y_out: OUT std_logic_VECTOR(7 downto 0);
		rdy: OUT std_logic;
		clk: IN std_logic);
	end component;

	signal p0_in_i,p1_in_i,p2_in_i,p3_in_i: UNSIGNED (7 downto 0);
	signal p0_out_i,p1_out_i,p2_out_i,p3_out_i: UNSIGNED (7 downto 0);

	signal x_in_i,y_in_i: std_logic_vector(7 downto 0);
	signal x_out_i,y_out_i,phase_in_i: std_logic_vector (7 downto 0);
	signal c_rdy,c_nd: std_logic;

	signal int_tx_no_usada,int_rx_no_usada: std_logic;											 	
	signal stb,ack: std_logic;
	signal we: std_logic;
	signal adr: std_logic_vector(1 downto 0);
	signal data_in,data_out: std_logic_vector(7 downto 0);

begin


	P_DP<='1'; -- Nunca se activan
	P_AN3<='1';
	P_AN2<='1';

--Inst_UART: UART generic map(BRDIVISOR => 1300) -- 9600baudios y 50Mhz
Inst_UART: UART generic map(BRDIVISOR => 325) -- 9600baudios y 12,5Mhz			 
			 port map(clk_out,not(rst_lo),adr,data_in,data_out,we,stb,ack,
			 		int_tx_no_usada,int_rx_no_usada,clk_out,TX,RX);


	(stb,c_nd,P_LD7,P_AN1,P_AN0)<=p0_out_i(5 downto 1);
	we<=p0_out_i(7);
	adr<='0' & p0_out_i(6);

MUX: process(clk_out)
begin
	if clk_out'event and clk_out='1' then
		if p0_out_i(0)='0' then
			(P_A,P_B,P_C,P_D,P_E,P_F,P_G)<=p1_out_i(7 downto 1);		
			data_in<=conv_std_logic_vector(p2_out_i,8);
		else
		-- Modo CORDIC
			x_in_i<=conv_std_logic_vector(p1_out_i,8);		
			y_in_i<=conv_std_logic_vector(p2_out_i,8);		
		end if;
	end if;
end process;

	p0_in_i<=(ack & c_rdy & P_BTN2 & P_BTN1 & P_BTN0 & "000");
	p1_in_i<=unsigned(x_out_i);
	p2_in_i<=unsigned(y_out_i);
	p3_in_i<=unsigned(data_out);

	phase_in_i<=conv_std_logic_vector(p3_out_i,8);
	
Inst_8051: I8051_ALL
	port map (rst_lo => rst_lo, 
         clk => clk_out,       
	    p0_in =>  p0_in_i, 
         p0_out => p0_out_i, 
         p1_in  => p1_in_i,    
         p1_out => p1_out_i,   
         p2_in  => p2_in_i,    
         p2_out => p2_out_i,    
         p3_in  => p3_in_i,
         p3_out => p3_out_i
	);

	Inst_clk_div: clk_div PORT MAP(
		RST_IN => rst_externo,
		CLKIN_IN => clk,
		LOCKED_OUT => rst_lo,
		CLKDV_OUT => clk_out,
		CLK0_OUT => clk0,
		CLKIN_IBUFG_OUT => c
	);

U0 : cordic
		port map (
			x_in => x_in_i,
			y_in => y_in_i,
			phase_in => phase_in_i,
			nd => c_nd,
			x_out => x_out_i,
			y_out => y_out_i,
			rdy => c_rdy,
			clk => clk_out);


end Behavioral;
