--
-- Copyright (c) 2001 Koay Kah Hoe.  Permission to copy is granted
-- provided that this header remains intact.  This code is provided
-- with no warranties.
--
-- Version : 1.0
--

-------------------------------------------------------------------------------

-- Bin_Onehot_Decoder: Library module created by VHDL Module Generator
--
-- Bin_Onehot_Decoder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity DataMask is
	generic (
		InWidth: integer:= 3
	);
	port (
		BinIn: in UNSIGNED(InWidth-1 downto 0);
		EN: in STD_LOGIC;
		DecOut: out STD_LOGIC_VECTOR(2**InWidth-1 downto 0)
	);
end DataMask;

architecture DataMask_arch of DataMask is

begin

	process (BinIn,EN)
		constant len: INTEGER := 2**InWidth;
		variable S:UNSIGNED (len-1 downto 0);
		variable iA: integer range 0 to len-1;
	begin
		S := (others=>not('0'));
		if EN = '1' then
			iA := CONV_INTEGER(BinIn);
			S(0) := '0';
			for I in 0 to len-1 loop
				if I < iA then
					S := SHL(S,"1");
					S(0) := not('0');
				end if;
			end loop;
		end if;
		DecOut <= CONV_STD_LOGIC_VECTOR(S,len);
	end process;

end DataMask_arch;

