--
-- Copyright (c) 2001 Koay Kah Hoe.  Permission to copy is granted
-- provided that this header remains intact.  This code is provided
-- with no warranties.
--
-- Version : 1.0
--

-------------------------------------------------------------------------------
-- RAM16Xn
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAM16XnS is
	generic (
		DataWidth: integer:= 8
	);
	port (
		D: in UNSIGNED(DataWidth-1 downto 0);
		A: in UNSIGNED(3 downto 0);
		WE,WCLK : in STD_LOGIC;
		O : out UNSIGNED(DataWidth-1 downto 0)
	);
end RAM16XnS;

architecture RAM16XnS_arch of RAM16XnS is

	component RAM16X1S
	port (
		D, A3, A2, A1, A0, WE, WCLK : in STD_LOGIC;
		O : out STD_LOGIC
	);
	end component;

begin
	U1: for I in 0 to DataWidth-1 generate
		U_RAM16X1S: RAM16X1S
			port map (D(I), A(3), A(2), A(1), A(0), WE, WCLK, O(I));
	end generate;
end RAM16XnS_arch;

